About PCB over hole, some things have to be said ...... | Fast turn PCB

First, what is over-hole

Through-hole (via) is one of the important components of multilayer PCB, the cost of drilling usually accounts for 30% to 40% of the cost of PCB board making. Simply put, each hole on the PCB can be called a hole. From a role perspective, vias can be divided into two categories: one is used as an electrical connection between the layers; the second is used to fix or position the device. If you look at the process, the holes are generally divided into three categories, namely, blind holes, buried holes and through holes.

Blind holes are located in the top and bottom surface of the printed circuit board, with a certain depth, for the connection between the surface layer of the line and the following inner layer of the line, the depth of the hole usually does not exceed a certain ratio (hole diameter).

Buried holes are connection holes located in the inner layer of the printed wiring board, which do not extend to the surface of the board. Both of these types of holes are located in the inner layers of the circuit board, and are completed using the through-hole forming process before lamination, and may overlap to make several inner layers during the over-hole formation process.

Through-holes, which pass through the entire board, can be used to achieve internal interconnections or as mounting and positioning holes for components. Since through-hole is easier to implement in the process and less expensive, it is used in the vast majority of printed circuit boards instead of the other two types of vias. The following said over-hole, no special instructions, are considered as through-hole.

Second, the composition of the hole

From the design point of view, a hole consists of two main parts, one is the middle of the hole, the second is the pad area around the hole. The size of these two parts determine the size of the vias. Obviously, in high-speed, high-density PCB design, the designer always wants the smaller the hole the better, so that the board can leave more wiring space, in addition, the smaller the hole, its own parasitic capacitance is also smaller, more suitable for high-speed circuits.

The smaller the hole, the longer it takes to drill the hole and the easier it is to deviate from the center; and when the depth of the hole is more than 6 times the diameter of the hole, it is impossible to ensure that the hole walls are evenly plated with copper. For example, the thickness of a normal 6-layer PCB board (through-hole depth) is about 50Mil, so PCB manufacturers can provide the minimum drilling diameter can only reach 8Mil.

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Third, the parasitic characteristics of the through-hole

1 Parasitic capacitance

Over-hole itself there is a parasitic capacitance to the ground, if it is known over-hole in the layered isolation hole diameter D2, over-hole pad diameter D1, PCB board thickness T, the board substrate dielectric constant ε, the size of the parasitic capacitance of the over-hole is approximated by

C=1.41εTD1/(D2-D1)

The main effect of the parasitic capacitance of the vias on the circuit is that it lengthens the rise time of the signal and reduces the speed of the circuit.

For example, for a PCB board thickness of 50Mil, if the use of the inner diameter of 10Mil, pad diameter of 20Mil over-hole, pad and ground copper laying area distance of 32Mil, then we can approximate the parasitic capacitance of the over-hole by the above formula is roughly

C=1.41×4.4×0.050×0.020/(0.032-0.020)=0.517pF

The amount of rise time change due to this part of capacitance is

T10-90=2.2C(Z0/2)=2.2×0.517x(55/2)=31.28ps

From these values, it can be seen that although the utility of the rise delay slowdown caused by the parasitic capacitance of a single vias is not very obvious, the designer should still consider carefully if the vias are used several times in the alignment for switching between layers.

2 Parasitic inductance

In the design of high-speed digital circuits, the parasitic inductance of the vias often brings more harm than the parasitic capacitance. Its parasitic series inductance can weaken the contribution of the bypass capacitor and diminish the filtering utility of the entire power system. We can simply calculate the parasitic inductance of an over-hole approximation using the following equation.

L=5.08h[ln(4h/d)+1]

where L refers to the inductance of the vias, h is the length of the vias, and d is the diameter of the center borehole.

As can be seen from the equation, the diameter of the vias has a small effect on the inductance, while the length of the vias has the greatest effect on the inductance. Still using the above example, the inductance of the vias can be calculated as

L=5.08×0.050[ln(4×0.050/0.010)+1]=1.015nH

If the rise time of the signal is 1ns, then the equivalent impedance size is

XL=πL/T10-90=3.19Ω

Such an impedance can no longer be ignored when there is a high frequency current passing through, especially note that the bypass capacitor needs to pass through two vias when connecting the power and ground layers, so that the parasitic inductance of the vias will increase exponentially.

IV. Tips for designing overholes

Designing vias in high-speed PCBs Through the above analysis of the parasitic characteristics of vias, we can see that the seemingly simple vias in high-speed PCB design can often have a significant negative effect on the design of the circuit. In order to reduce the negative impact of the parasitic effect of vias, one can try to do the following in the design:

1. Choose a reasonably sized vias size in terms of both cost and signal quality. For example, for 6-10 layer memory module PCB design, it is better to choose 10/20Mil (drill/pad) vias, and for some high density small size boards, you can also try to use 8/18Mil vias.

Current technology makes it difficult to use smaller size vias. For power or ground vias, consider using a larger size to reduce impedance.

2. The two equations discussed above lead to the conclusion that the use of thinner PCBs facilitates the reduction of both parasitic parameters of the vias.

3. Try not to change layers of the signal alignment on the PCB, which means try not to use unnecessary vias.

4. The power and ground pins should be punched close together, and the shorter the leads between the vias and pins, the better, as they can cause an increase in inductance. Also the power and ground leads should be as thick as possible to reduce impedance.

5. Place some grounded vias near the signal commutation vias to provide the closest circuit for the signal. You can even place some extra grounded vias in large numbers on the PCB. Of course, in the design also needs to be flexible and versatile. The vias model discussed earlier is a case where each layer has pads, but there are times when we can reduce or even remove the pads on some layers.

Particularly in the case of very dense vias, which can lead to a broken slot in the copper layup layer that isolates the loop, to solve such a problem in addition to moving the location of the vias, we can also consider reducing the size of the pads of the vias in that layup layer.