Most of the high-speed design theories have to be finally implemented and verified by Layout, which shows that wiring is crucial in high-speed PCB design. The following will analyze the rationality of some situations that may be encountered in the actual wiring, and give some more optimized alignment strategies.

The main three aspects are right-angle alignment, differential alignment, and serpentine alignment.

Right-angle alignment Right-angle alignment is generally required in PCB cabling to avoid the situation as far as possible, but also almost become one of the criteria for measuring good or bad cabling, then right-angle alignment will actually have how much impact on signal transmission? In principle, right-angle alignment will make the transmission line width changes, resulting in discontinuity of impedance. In fact, not only right-angle alignment, obtuse angle, acute angle alignment may cause impedance changes.

Right-angle alignment of the impact on the signal is mainly reflected in three areas.

First, the corner can be equivalent to the capacitive load on the transmission line, slowing down the rise time.

Second, the impedance discontinuity will cause the reflection of the signal.

The third is the EMI generated by the right-angle tip.

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The parasitic capacitance from the right angle of the transmission line can be calculated by the following empirical formula.

C = 61W (Er)1/2/Z0

In the above equation, C is the equivalent capacitance of the corner (in pF), W refers to the width of the alignment (in inch), εr refers to the dielectric constant of the dielectric, and Z0 is the characteristic impedance of the transmission line. As an example, for a 4 Mils 50 Ohm transmission line (εr of 4.3), a right angle brings a capacitance of roughly 0.0101 pF, and thus the resulting rise time variation can be estimated as

T10-90% = 2.2CZ0/2 = 2.20.010150/2 = 0.556ps

The calculation shows that the capacitive effect of right-angle alignment is extremely small.

As the line width of the right-angle alignment increases, the impedance there will be reduced, so there will be a certain signal reflection phenomenon, we can calculate the equivalent impedance after the increase in line width according to the impedance calculation formula mentioned in the chapter on transmission lines, and then calculate the reflection coefficient according to the empirical formula

ρ = (Zs – Z0) / (Zs + Z0)

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The general right-angle alignment results in an impedance change of between 7% and 20%, and thus the reflection coefficient is about 0.1 at maximum. Moreover, as can be seen from the figure below, the impedance of the transmission line changes to a minimum within the time of W/2 line length, and then returns to normal impedance after W/2 time, the entire impedance change occurs in a very short period of time, often within 10 ps, such a fast and small change in the general signal transmission is almost negligible.

Many people have an understanding that right-angle alignments tend to emit or receive electromagnetic waves and generate EMI, which is one of the reasons why many people believe that right-angle alignments should not be used. The results of many actual tests show that right-angle alignment does not produce very significant EMI than straight lines. perhaps the current instrument performance, test level constraints on the accuracy of the test, but at least it shows a problem, right-angle alignment of radiation has been less than the measurement error of the instrument itself.    

In general, right-angle alignments are not as terrible as one might think. At least in sub-GHz applications, any effects such as capacitance, reflection, EMI, etc. are barely noticeable in TDR testing, and the focus of high-speed PCB design engineers should still be on layout, power/ground design, alignment design, vias, and other aspects. Of course, although the impact of right-angle alignment is not very serious, but it does not mean that we can go right-angle lines in the future, attention to detail is the basic quality of every good engineer, and, with the rapid development of digital circuits, PCB engineers deal with the signal frequency will continue to improve, to 10GHz RF design field, these small right angles may become high-speed problems focus.

2. Differential Alignment    Differential Signal (Differential Signal) in high-speed circuit design is becoming more and more widely used, the most critical signals in the circuit are often designed using differential structure, what another it is so popular? In the PCB design and how to ensure its good performance? With these two questions in mind, let’s take the next part of the discussion.

What is a differential signal? In layman’s terms, it means that the driver sends two equal and opposite signals, and the receiver determines the logic state “0” or “1” by comparing the difference between the two voltages. The pair of alignments that carry the differential signals are called differential alignments.    

The most obvious advantages of differential signals over normal single-ended signal alignments are in the following three areas:   

a. High immunity to interference because the coupling between the two differential alignments is so good that when outside noise interference exists, it is coupled to both lines almost simultaneously, and all that matters at the receiving end is the difference between the two signals, so outside common mode noise can be completely canceled out.    

b. It can effectively suppress EMI, by the same token, since the polarity of the two signals are opposite, their outwardly radiated electromagnetic fields can cancel each other out, and the tighter the coupling, the less electromagnetic energy will be leaked to the outside world.    

c. Precise timing positioning, because differential signals change at the intersection of two signals, unlike normal single-ended signals that rely on both high and low threshold voltages, is less affected by process, temperature, and can reduce timing errors, and is also better suited for low amplitude signal circuits. The currently popular LVDS (low voltage differential signaling) refers to this small amplitude differential signaling technique.    

For PCB engineers, the biggest concern is still to ensure that these advantages of differential alignment are fully utilized in the actual alignment. Perhaps anyone who has worked with Layout will understand the general requirement for differential alignments, which is “equal length, equal spacing”. Equal length is to ensure that the two differential signal always maintain the opposite polarity, reducing the common mode component; isometric is mainly to ensure that the two differential impedance consistent, reducing reflections. The “as close as possible principle” is sometimes one of the requirements of the differential alignment. But all these rules are not used to apply, many engineers do not seem to understand the nature of high-speed differential signal transmission.    

The following discussion focuses on several common misconceptions in PCB differential signal design.    

Misconception 1: The belief that differential signals do not require a ground plane as a return path, or that differential alignments provide return paths for each other. The reason for this misconception is that we are either confused by superficial phenomena or do not have a deep enough understanding of the mechanics of high-speed signal transmission. As can be seen from the structure of the receiver side of Figure 1-8-15, the emitter currents of transistors Q3, Q4 are equal and reversed, and their currents at the junction exactly cancel each other (I1=0), thus the differential circuit is insensitive to similar ground bounces and other noise signals that may be present in the power and ground planes. Ground plane part of the return current offset does not mean that the differential circuit does not take the reference plane as the signal return path, in fact, in the signal return analysis, differential alignment and ordinary single-ended alignment mechanism is the same, that is, the high-frequency signal is always along the inductance of the smallest loop for the return, the biggest difference is that the differential line in addition to the coupling to ground, there is also mutual coupling, which is a strong coupling, that one will becomes the main return circuit. Figure 1-8-16 shows the geomagnetic field distribution for a single-ended signal and a differential signal.

In PCB circuit design, the coupling between differential alignments is generally small, often accounting for only 10-20% of the coupling, and more of the coupling to ground, so the main return path for differential alignments still exists in the ground plane. When the ground plane discontinuity occurs, the region without the reference plane, the coupling between the differential alignment will only provide the main return path, see Figure 1-8-17 shows. Although the impact of the reference plane discontinuity on the differential alignment is not as severe as on a normal single-ended alignment, it can still degrade the quality of the differential signal and increase EMI, and should be avoided. Some designers believe that the reference plane below the differential alignment can be removed to suppress part of the common mode signal in the differential transmission, but from a theoretical point of view this practice is not desirable, how to control the impedance? Not providing a ground impedance loop to the common mode signal is bound to cause EMI radiation, and this practice does more harm than good.

Misconception #2: It is more important to maintain equal spacing than to match line lengths. In actual PCB routing, the requirements of differential design are often not met at the same time. Due to the pin distribution, vias, and alignment space, proper winding is necessary to achieve the purpose of wire length matching, but the result is inevitably that some areas of the differential pair cannot be parallel, so how do we make the trade-off? Before we jump to conclusions, let’s take a look at the following simulation results.

From the simulation results above, it appears that the waveforms of Scenario 1 and Scenario 2 almost overlap, meaning that the effect of the spacing mismatch is negligible, compared to the much larger effect of the line length mismatch on the timing (Scenario 3). Then from the theoretical analysis, although the spacing inconsistency will lead to changes in differential impedance, but because the coupling between the differential pair itself is not significant, so the impedance change range is also very small, usually within 10%, only equivalent to a reflection caused by the hole, which does not cause significant impact on signal transmission. In contrast, once the line lengths are mismatched, in addition to timing shifts, they also introduce a common mode component into the differential signal, degrading the signal quality and increasing EMI.    

So to speak, the most important rule in the design of PCB differential alignments is to match the line length, all other rules can be flexible based on design requirements and practical applications.    

Mistake #3: Thinking that differential alignments must be close together. Having differential alignments close together is simply to enhance their coupling, both to improve immunity to noise and to take advantage of the opposite polarity of the magnetic field to offset EMI to the outside world. Although this practice is very beneficial in most cases, but not absolutely, if we can ensure that they are adequately shielded from external interference, then we do not need to let through each other’s strong coupling to achieve the purpose of anti-interference and EMI suppression. How can we ensure that the differential alignment with good isolation and shielding? Increase the spacing with other signal lines is one of the most basic ways, electromagnetic field energy is a square relationship with the distance decreases, the general line spacing of more than 4 times the line width, the interference between them is extremely weak, basically can be ignored. In addition, isolation through the ground plane can also provide excellent shielding, a structure often used in high frequency (10G+) IC package PCB designs, called CPW structures, which ensure tight differential impedance control (2Z0), as shown in Figure 1-8-19.

Differential alignments can also be run in different signal layers, but this is generally not recommended because differences such as impedance and vias from different layers can disrupt differential mode transmission and introduce common mode noise. In addition, if the adjacent two layers are not coupled closely enough, it will reduce the ability of the differential alignment to resist noise, but if you can maintain the appropriate spacing with the surrounding alignment, crosstalk is not a problem. In general frequency (GHz below), EMI will not be a very serious problem, experiments show that the distance between 500Mils differential alignment, in 3 meters away from the radiation energy attenuation has reached 60dB, enough to meet the FCC’s electromagnetic radiation standards, so designers simply do not have to worry too much about the differential line coupling is not enough to cause electromagnetic incompatibility problems.

3. Serpentine   

Snake lines are a class of alignment often used in Layout. Its main purpose is to adjust the delay to meet the system timing design requirements. Designers first need to have the understanding that snake lines can damage the signal quality and change the transmission delay, so they should be avoided as much as possible when wiring. However, in practice, the design often has to be wound intentionally to ensure sufficient hold time for the signal, or to reduce the time offset between the same group of signals.

So, how does snaking the wire affect signal transmission? What do you need to be aware of when routing? Two of the most critical parameters are the parallel coupling length (Lp) and the coupling distance (S), as shown in Figure 1-8-21. Obviously, when the signal is transmitted on the serpentine alignment, coupling will occur between the mutually parallel line segments in the form of differential modes, the smaller the S, the larger the Lp, the greater the degree of coupling. This may lead to a reduction in transmission delay, as well as a significant degradation of the signal quality due to crosstalk, the mechanism of which can be found in the analysis of common mode and differential mode crosstalk in Chapter 3.

Here are a few suggestions for Layout engineers when dealing with serpentines:   

  1. Try to increase the distance (S) of parallel line segments to at least greater than 3H, with H referring to the distance of the signal alignment to the reference plane. In layman’s terms, this means going around large bends, and as long as S is large enough, mutual coupling effects can be almost completely avoided.    
  2. Reducing the coupling length Lp, the resulting crosstalk will saturate when twice the Lp delay approaches or exceeds the signal rise time.    
  3. Strip-Line or Embedded Micro-strip serpentine lines cause less signal transmission delay than Micro-strip. In theory, a strip line will not affect the transmission rate due to differential mode crosstalk.    
  4. High-speed and more stringent timing requirements of the signal line, try not to take the snake line, especially not in a small area of meandering alignment.    
  5. Any angle snake alignment can often be used, such as the C structure in Figure 1-8-20, which can effectively reduce the coupling between each other.    
  6. In high speed PCB design, snake lines have no so-called filtering or anti-interference capability and may only degrade the signal quality, so they are only used for timing matching and no other purpose.    
  7. Sometimes a spiral alignment can be considered for winding, and simulations have shown that it is better than a normal serpentine alignment.