Design guidelines for mixed-signal boards | Fast turn PCB

Analog circuits rely on continuously varying currents and voltages for their operation. The operation of a digital circuit depends on the detection of a high or low level at the receiver according to a predefined voltage level or threshold, which is equivalent to determining whether the logic state is “true” or “false”. In the digital circuit between the high and low levels, there is a “gray” area, where the digital circuit sometimes exhibits analog effects, such as when jumping from low to high (state), if the digital signal jumps fast enough, it will produce overshoot and ringback reflections.      

    The concept of mixed-signal PCBs is vague for modern board-pole design because analog circuits and analog effects are still present even in purely “digital” devices. Therefore, in the early stages of design, in order to reliably achieve strict timing distribution, the analog effects must be simulated. In fact, in addition to communications products that must be reliable for years of trouble-free operation, simulation of analog effects is especially needed in mass-produced low-cost/high-performance consumer products.

    Another difficult aspect of modern mixed-signal PCB design is the increasing number of devices with different digital logic, such as GTL, LVTTL, LVCMOS and LVDS logic, each with different logic thresholds and voltage swings, but these different logic thresholds and voltage swings must be designed together on a single PCB. By thoroughly analyzing the layout and wiring design of high density, high performance, mixed signal PCBs, you are equipped with the strategies and techniques to succeed.

    Mixed-Signal Circuit Wiring Fundamentals

    When digital and analog circuits share the same components on the same board, the layout and wiring of the circuit must be methodical.

    In mixed-signal PCB designs, there are special requirements for power supply routing and the need to isolate analog and digital circuit noise from each other to avoid noise coupling, which increases the complexity of layout and routing. The special need for power supply routing and the requirement to isolate noise coupling between analog and digital circuits adds further complexity to the layout and routing of mixed-signal PCBs.

    If the power supply for the analog amplifier in the A/D converter and the digital power supply for the A/D converter are connected together, there is a high probability that the analog and digital parts of the circuit will interact. Perhaps the layout scheme must mix the wiring of the digital and analog circuits because of the input/output connector locations.

    Before layout and wiring, engineers need to figure out the basic weaknesses of the layout and wiring scheme. Even if there are false judgments, most engineers tend to use the layout and wiring information to identify potential electrical impacts.

    Layout and routing of modern mixed-signal PCBs

    The following will illustrate mixed-signal PCB layout and cabling techniques through the design of the OC48 interface card. OC48 stands for Optical Carrier Standard 48 and is essentially geared towards 2.5Gb serial optical communications, which is one of the high-capacity optical communications standards for modern communications equipment.The OC48 interface card contains several typical mixed-signal The OC48 interface card contains several typical mixed-signal PCB layout and routing problems, and its layout and routing process will indicate the sequence and steps to solve the mixed-signal PCB layout solution.

The OC48 card contains an optical transceiver that implements bidirectional conversion of optical and analog electrical signals. Analog signals are input or output to a digital signal processor, and the DSP converts these analog signals to digital logic levels so that they can be interfaced with the microprocessor, programmable gate array, and the system interface circuitry between the DSP and microprocessor on the OC48 card. A separate phase-locked loop, power supply filter, and local reference voltage source are also integrated.

    Where the microprocessor is a multi-power device with a 2V main power supply and 3.3V I/O signal power shared by other digital devices on the board. A separate digital clock source clocks the OC48I/O, microprocessor, and system I/O.

    After examining the layout and wiring requirements of the different functional circuit blocks, a 12-layer board was initially recommended. The configuration of microstrip and ribbon line layers safely reduces coupling of adjacent alignment layers and improves impedance control. A grounding layer between the first and second layers will isolate the wiring of sensitive analog reference sources, CPU cores and PLL filter power supplies from the microprocessor and DSP devices at the first layer. The power and ground layers always appear in pairs, the same as on the OC48 card for the shared 3.3V power layer. This will reduce the impedance between power and ground, thus reducing noise on the power signal.

    Avoid running digital clock lines and high-frequency analog signal lines adjacent to the power supply layer; otherwise, noise from the power supply signal will couple into the sensitive analog signal.

    Careful consideration should be given to utilizing openings in the power and analog ground layers (splits) as needed for digital signal wiring, especially at the input and output of mixed signal devices. In the adjacent signal layer across an opening alignment will cause impedance discontinuities and poor transmission line loops. These can cause signal quality, timing, and EMI problems.

    Sometimes adding several grounding layers, or using several peripheral layers underneath a device for either the local power or grounding layer, can eliminate openings and avoid these problems, as was done with the OC48 interface card with multiple grounding layers. Maintaining symmetry in the placement of the opening and wiring layers can avoid card distortion and simplify the fabrication process. Due to the high current tolerance of 1 oz. copper-clad boards, the 3.3V power supply layer and corresponding ground layer should be 1 oz. copper-clad, and the other layers can be 0.5 oz. copper-clad, which reduces voltage fluctuations caused by transient high currents or during spikes.

    If you are designing a complex system from the grounding layer up, cards of 0.093″ and 0.100″ thickness should be used to support the wiring layer and the ground isolation layer. The thickness of the card must also be sized to the over-hole pads and wiring characteristics of the holes so that the width-to-height ratio of the drilled hole diameter to the finished card thickness does not exceed the width-to-height ratio of the metalized holes provided by the manufacturer.

    If a low-cost, high-volume commercial product is to be designed with a minimum number of wiring layers, carefully consider the wiring details for all special power supplies on a mixed-signal PCB before laying out or wiring. Before starting layout and wiring, have the target manufacturer review the initial layering scheme. Basically, layering should be based on finished product thickness, number of layers, copper weight, impedance (with tolerances) and minimum over-hole pads and hole sizes, and the manufacturer should provide layering recommendations in writing.

    The proposal should include examples of all configurations of controlled impedance ribbon and microstrip lines. To consider your predictions of impedance in conjunction with the manufacturer’s predictions of impedance, these impedance predictions can then be used to verify the signal wiring characteristics in the simulation tool used to develop the CAD wiring rules.

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    The high-speed analog signals between the optical transceiver and the DSP are very sensitive to external noise. Likewise, all the special power supply and reference voltage circuitry creates a lot of coupling between the card’s analog and digital power delivery circuits. Sometimes, the shape of the enclosure forced the design of a high density board card. The orientation of the external fiber optic cable into the card and the high component size of the optical transceiver section caused the transceiver to be largely immobilized in the card. The system I/O connector locations and signal assignments were also fixed. This is the groundwork that must be completed prior to layout.

    As with most successful high-density analog layout and cabling schemes, the layout has to meet the cabling requirements, and the layout and cabling requirements have to be balanced with each other. For a mixed-signal PCB analog part and 2V operating voltage of the local CPU core, not recommended to use the “layout first and then wiring” approach. For the OC48 card, the DSP analog circuitry section containing the analog reference voltage and analog power bypass capacitors should be wired interactively first. After the wiring is completed, the entire DSP with analog components and wiring should be placed close enough to the optical transceiver to fully ensure that the wiring length of the high-speed analog differential signal to the DSP is the shortest, with the fewest bends and vias. The symmetry of the differential layout and cabling will reduce the effect of common mode noise. However, it is difficult to predict the best solution for the layout prior to cabling.

    Be sure to consult your chip distributor for PCB layout design guidelines. Talk fully with the distributor’s application engineers before designing according to the guidelines. Many chip distributors have strict time limits for providing high-quality layout advice. Sometimes, they provide solutions for the use of the device “Tier 1 customers” is feasible. In the area of signal integrity (SI) design, the signal integrity design of new devices is particularly important. By following the distributor’s basic guidelines and combining them with the specific requirements for each power and ground pin in the package, you can start wiring the OC48 card with the integrated DSP and microprocessor.

    Once the location and wiring of the high frequency analog section is determined, the rest of the digital circuitry can be placed. Careful attention should be paid to the careful design of the following circuits: the location of the PLL power filter circuit in CPUs with high sensitivity to analog signals; the local CPU core voltage regulator; and the reference voltage circuit for the “digital” microprocessor.

    The electrical and manufacturing code specifications for digital cabling can only be properly applied to the design at this time. The aforementioned design for signal integrity of high-speed digital buses and clock signals reveals some special wiring topology requirements for processor buses, balanced Ts, and time lag matching of certain clock signal wiring. But what you may not know is that newer suggestions have also been made to add several termination resistors.

    It is a matter of course to make some adjustments during the layout phase of the problem solving process. However, before you start wiring, a very important step is to verify the timing of the digital part according to the layout plan. At this point in time, a complete DFM/DFT layout review of the board will help ensure that the card meets the customer’s needs.

    Digital wiring for OC48 cards

    For digital device power lines and digital parts of mixed-signal DSPs, digital cabling starts with SMD way-out diagrams (escape patterns). To use the assembly process allows the shortest and widest printed lines. For high-frequency devices, the power supply print line is equivalent to a small inductor, it will worsen the power supply noise, so that the analog and digital circuits between the undesired coupling. The longer the power supply print line, the greater the inductance.

    Optimal layout and wiring solutions are available with digital bypass capacitors. In short, the bypass capacitors are fine-tuned as needed for easy installation and distribution around the digital parts and digital sections of mixed-signal devices. The same “shortest and widest alignment” approach is used to route the bypass capacitor out of the way.

    When the power supply branch is to cross a contiguous plane (such as the 3.3V power supply layer on the OC48 interface card), the power supply pins and the bypass capacitor itself do not have to share the same exit map to get the lowest inductance and ESR bypass. On a mixed-signal PCB like the OC48 interface card, pay special attention to the wiring of the power supply branches. Remember to place additional bypass capacitors in a matrix arrangement across the card, even near passive devices

    Once the power outlet diagram is determined, the autowiring can begin. ATE test contacts on the OC48 card are to be defined at logic design time. Be sure that the ATE contacts 100% of the nodes. To achieve ATE testing with a minimum ATE test probe of 0.070″, the location of the lead-out via must be preserved to ensure that the power supply layer is not interrupted by the reverse pad (antipads) crossing of the via.

    If a power and ground layer opening (split) scheme is to be used, the offset layer (layer bias) should be selected on the adjacent wiring layer parallel to the opening. A no-wiring zone is defined on the adjacent layer by the perimeter of the opening area to prevent wiring from entering. If cabling must pass through the opening to another layer, ensure that the other layer adjacent to the cabling is a continuous grounding layer. This will reduce the reflection path. Having bypass capacitors across the open power layer is good for some digital signal layouts, but bridging between the digital and analog power layers is not recommended because noise can be coupled to each other through the bypass capacitors.

    Several recent automated routing applications enable the routing of high-density multilayer digital circuits. The initial routing phase involves using a large 0.050-inch vias spacing in the SMD exit and considering the type of package used. The subsequent routing phase allows the vias to be positioned closer to each other so that all tools achieve the highest fabric throughput and lowest vias count. Because the OC48 processor bus uses a modified star topology, it has the highest priority when it comes to automated routing.

    Summary

    Signal integrity verification and timing simulations are performed after the OC48 card layout is complete. The simulation proves that the wiring guidance meets the expected requirements and improves the timing metrics of the Layer 2 bus. The final design rule check, final manufacturing review, photomask and review, and issuance to the fabricator are the official end of the board layout task.

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